Liquid crystal display devices using an active matrix system are widely used in for example liquid crystal projector apparatus, liquid crystal display apparatus and the like. FIG. 6 shows an example of circuit configuration of such a liquid crystal display device 100 using the active matrix system. As is well known, a liquid crystal display device using the active matrix system has pixel cell driving circuits each having a pixel switch and a pixel capacitance connected to the pixel switch, for example, which circuits are formed so as to be arranged in a form of a matrix on a semiconductor substrate. The liquid crystal display device also has a structure in which a counter substrate having a common electrode formed thereon is opposed to the semiconductor substrate and a liquid crystal is sealed in between the semiconductor substrate and the counter substrate.
As shown as a pixel cell driving circuit 10 in a part enclosed by a broken line in FIG. 6, for example, each of the pixel cell driving circuits formed on the semiconductor substrate has a pixel switch S11, a pixel capacitance C11, and a pixel electrode P11. In this case, an N-channel type FET (Field Effect Transistor) is used as the pixel switch. The pixel switch S11 has a source connected to a common electrode (or a ground) via the pixel capacitance C11. A node of the source of the pixel switch S11 and the pixel capacitance C11 is connected. with a pixel electrode P11. Incidentally, a “pixel cell” in the liquid crystal display device refers to a display region in a liquid crystal layer corresponding to each such pixel electrode. The pixel switch S11 has a gate connected with a gate line G1 extended from a vertical scanning circuit 2, and has a drain connected with a data line D1 extended from a horizontal scanning circuit 3. One pixel cell driving circuit is thus formed, and the pixel cell driving circuits are arranged in the form of the matrix on the semiconductor substrate as shown in FIG. 6.
The vertical scanning circuit 2 and the horizontal scanning circuit 3 each including a shift register, for example, are also formed on the semiconductor substrate. The vertical scanning circuit 2 sequentially scans gate lines G1, G2, . . . Gv extended in a horizontal direction. The horizontal scanning circuit 3 sequentially scans data lines D1, D2, D3 to Dh extended in a vertical direction.
The counter substrate having the common electrode supplied with a common potential Vcom is disposed so as to be opposed to the thus formed semiconductor substrate. The liquid crystal is sealed in between the semiconductor substrate 100 and the counter substrate disposed in such opposed positional relation to each other, whereby a liquid crystal layer 5 is formed. The liquid crystal display device 100 as a whole has such a structure.
FIGS. 7(a) to 7(j) are timing charts illustrating timing of driving pixel cells in the liquid crystal display device 100 with the above-described structure. The vertical scanning circuit 2 shifts an output thereof by one line by the shift register. Thereby the vertical scanning circuit 2 scans the gate lines in a vertical direction in order of the gate lines G1→G2→G3→ . . . on a line-sequential basis, as shown in FIGS. 7(a), 7(b), and 7(c). As shown in the figures, a power supply voltage VDD is applied to a gate line in a scanning period. In this period, a pixel switch connected to the gate line is in an on state. While scanning is not performed, the gate line is set to a ground potential VSS, and thus the pixel switch is in an off state.
FIG. 7(d) shows in enlarged dimension a section A in which scanning of the gate line G1 as shown in FIG. 7(a) is started. When the scanning of the gate line G1 is started as shown in FIG. 7(d), the pixel switches S11 to S1h arranged in a row connected to the gate line G1 are all brought into the on state. Within the period when the gate line G1 is scanned, the horizontal scanning circuit 3 applies voltages V1, V2, V3, . . . corresponding to data to the data lines in order of the data lines D1→D2→D3→ . . . in a horizontal direction as shown in FIGS. 7(e) to 7(g). That is, the horizontal scanning circuit 3 performs scanning in the horizontal direction. The horizontal scanning circuit 3 sequentially shifts the data lines to which to apply an output thereof by the shift register, whereby the above operation is obtained.
First, when the data line D1 is scanned as shown in FIG. 7(e), a charge corresponding to a level of the voltage V1 is stored via the pixel switch S11 which is in the on state at this time. That is, data is written to one pixel. Thereby a potential corresponding to the charge stored occurs at the pixel capacitance C11. The potential is shown as a potential V1 corresponding to a voltage value V1.
The potential V1 also appears at the pixel electrode P11. In response to a potential difference between the potential V1 of the pixel electrode P11 and the common potential Vcom of the common electrode opposed thereto, the liquid crystal of the liquid crystal layer 5 corresponding to a position of the pixel electrode P11 is excited. That is, the pixel cell is driven. As is understood from timing of scanning the data line D1 in FIG. 7(e) and charge storing timing in FIG. 7(h), the charge stored in the pixel capacitance, that is, the data continues to be retained even after the scanning of one data line (data writing) is ended to shift to scanning of the next data line, and thus continues to excite the liquid crystal (pixel cell).
After the data line D1 is thus scanned, the data line D2 is scanned, as shown in FIG. 7(f). Similarly, data is written to a pixel capacitance C12 via a pixel switch S12, as shown in FIG. 7(i). Thereafter the next data line D3 is scanned as shown in FIG. 7(g), and as shown in FIG. 7(j), data is written to a pixel capacitance C12 via a pixel switch S12.
When the scanning in the horizontal direction of one row is completed and with this the scanning of the gate line G1 is also completed, scanning of the next gate line G2 is then started, as shown in FIG. 7(b). As described with reference to FIGS. 7(e) to 7(j), also within a period when the gate line G2 is scanned, scanning in the horizontal direction is performed, that is, data is written to pixel cells in a horizontal line corresponding to the gate line G2. Thereafter, in a state in which the next gate line G3 is scanned as shown in FIG. 7(c), data is written to pixel cells in a horizontal line corresponding to the gate line G3 in timing shown in FIGS. 7(e) to 7(j). Thereafter the remaining gate lines are sequentially scanned, and within a period of scanning of each gate line, data is similarly written to pixel cells in a horizontal line corresponding to the gate line. Thus the vertical scanning circuit 2 and the horizontal scanning circuit 3 in the liquid crystal display device using the active matrix system sequentially drive the pixel cells by scanning the gate lines so as to drive the gate lines sequentially and scanning the data lines so as to drive the data lines sequentially to write data within a period of scanning one gate line.
The semiconductor substrate forming the liquid crystal display device of the above configuration may have a failure or a defect formed in the circuits in its fabrication process. That is, the semiconductor substrate has a possibility that a pixel cell driving circuit not operating properly may exist because of a short circuit in the pixel switch or the pixel capacitance, a disconnection or a short circuit in the gate line or the data line, or the like. Thus the circuits on the semiconductor substrate are tested for defects in a process of fabricating the liquid crystal display device.
Such testing of the circuits on the semiconductor substrate for defects is performed as follows, for example. First the data lines extended from the semiconductor substrate to be tested and a testing device are connected to each other. On the semiconductor substrate, the vertical scanning circuit 2 and the horizontal scanning circuit 3 perform driving in timing similar to that at the time of display. Specifically, the vertical scanning circuit 2 and the horizontal scanning circuit 3 drive the pixel cells in the same manner as described with reference to FIGS. 7(a) to 7(j), for example. In this case, a data line connected to a pixel cell driving circuit to which data is written should have a potential at a level corresponding to the written data when the pixel cell driving circuit operates properly. When there is some defect, the potential level should be other than a normal value. Accordingly, the potential level is detected by the testing device, that is, charge of the pixel capacitance is read from the data line, whereby the pixel cell driving circuit can be tested for defects.
However, in consideration for use in for example projector apparatus and the like, the liquid crystal display device has recently been required to have reduced size and a larger number of pixels per unit area for improvement of resolution. In this case, when the size of the liquid crystal display device as a whole is to be reduced to ½ without changing the number of pixels, or when the resolution is to be doubled without changing the size of the device, for example, in both cases the longitudinal/lateral dimension of a pixel cell needs to be reduced to about ½. Assuming that the pixel cell has a square shape, when the longitudinal/lateral dimension of the pixel cell is to be reduced to ½, the pixel capacitance will be reduced to ¼.
For fabrication reasons, there is a limit to reduction in size of a pixel switch within a pixel cell driving circuit. Thus, when the size of the pixel switch is reduced to substantially a limit and the pixel cell needs to be further reduced in size, the pixel capacitance has to be reduced in size. Hence, when the pixel cell driving circuit is to be reduced to ½ the size thereof, for example, and when the size of the pixel switch is already considerably small, the size of the pixel capacitance needs to be reduced more to less than ¼, because a ratio of reduction in the size of the pixel capacitance is increased.
Considering capacitance of the data line, assuming that width in the lateral direction of the data line is not changed when the longitudinal/lateral dimension of the liquid crystal display device is to be reduced to ½, for example, only length in the longitudinal direction of the data line is reduced to ½, and the size of the data line as its area is reduced to ½. That is, the capacitance of the data line needs to be reduced by only ½. Thus, an imbalance in capacitance reduction rate occurs in that the pixel capacitance is reduced to ¼, whereas the capacitance of the data line is reduced only to ½.
Further, when the resolution is to be doubled without changing the size of the liquid crystal display device, the number of pixel switches connected to the data line is doubled even though the length of the data line is not changed. When the pixel switches cannot be reduced any further, the capacitance of the data line is increased by an amount corresponding to drain capacitance of the added pixel switches. Thus, as reduction in size of the pixel cell is furthered, a ratio of the data line capacitance to the pixel capacitance is increased, and so-called wiring capacitance becomes dominant. In such a case, when a charge of the pixel capacitance is to be read from the data line, a potential change in the data line may be so small as to be difficult to detect. Since the testing of the semiconductor substrate by the above-described method involves reading the charge of the pixel capacitance from the data line, it is difficult to conduct the test properly when the ratio of the wiring capacitance to the pixel capacitance is increased as described above.
Thus, in the present situation, it is required to actually display an image on a finished product as a liquid crystal display device after the filling of a liquid crystal, and then visually check the image, for example, to thereby test for pixel defects. When the test is thus conducted in a stage where the liquid crystal display device is completed, if a defect is found, for example, it is necessary to disassemble the liquid crystal display device and make repairs or discard the liquid crystal display device. That is, it is desirable from a viewpoint of fabrication efficiency and fabrication cost that the circuits formed on the semiconductor substrate be able to be tested in a stage where a wafer as the semiconductor circuit substrate is formed, for example, before being incorporated as the liquid crystal display device.
It is accordingly an object of the present invention to provide a semiconductor substrate testing method that properly detects a failure in pixel cell driving circuits before being completed as a semiconductor device even when the ratio of the wiring capacitance to the pixel capacitance is increased with decrease in size or increase in definition of the semiconductor device having the pixel cell driving circuits, a semiconductor device including a semiconductor substrate enabling the testing method, and a display apparatus having such a semiconductor device.